The present invention relates generally to semiconductor devices, and more particularly to copper interconnects and methods of their fabrication.
Manufacture of a semiconductor device is normally divided into two major phases. The “front end of the line” (FEOL) is dedicated to the creation of all the transistors in the body of the semiconductor device, and the “back end of the line” (BEOL) creates the metal interconnect structures, which connect the transistors to each other as well as provide power to the devices. The FEOL consists of a repeated sequence of steps that modifies the electrical properties of part of a wafer surface and grows new material above selected regions. Once all active components are created, the second phase of manufacturing (BEOL) begins. During the BEOL, metal interconnects are created to establish the connection pattern of the semiconductor device.
Semiconductor devices generally include a plurality of circuits which form an integrated circuit fabricated on a semiconductor substrate. To improve the performance of the circuits, low k dielectric materials, having a dielectric constant of less than silicon dioxide, are used between circuits as inter-layer dielectric (ILD) to reduce capacitance. Interconnect structures made of metal lines or metal vias are usually formed in and around the ILD material to connect elements of the circuits. Within a typical interconnect structure, metal lines run parallel to the semiconductor substrate, while metal vias run perpendicular to the semiconductor substrate. An interconnect structure may consist of multilevel or multilayered schemes, such as, single or dual damascene wiring structures.
There are many failure mechanisms that affect the reliability of an integrated circuit. Time Dependent Dielectric Breakdown (TDDB) is a failure mechanism where the dielectric material of the ILD breaks down as a result of long-time application of electrical stresses, such as high current density. The breakdown leads to formation of a conducting path through the dielectric material and between metal interconnects via surface diffusion of the metal interconnect structures, i.e., wires and vias. In time, the conducting path will form a short between interconnect structures causing a failure.